LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;


entity TP2 is
  port(
    ck: in std_logic; 
    d6: in std_logic;
    d5: out std_logic;
        
 salidaVGA4 : out std_logic_vector(3 downto 0);
 salidaVGA3 : out std_logic_vector(3 downto 0);
 salidaVGA2 : out std_logic_vector(3 downto 0);
 salidaVGA1 : out std_logic_vector(3 downto 0);
 
 displayNumerico : out std_logic_vector(7 downto 0);
 selector : out std_logic_vector(3 downto 0)
 
);
-- 			attribute loc: string;
			
--			attribute loc of ck: signal is "B8";
--			attribute loc of displayNumerico: signal is "L18 F18 D17 D16 G14 J17 H14 C17";
--			attribute loc of selector: signal is "F17 H17 C18 F15";
			
			
--			attribute loc of d6: signal is "K12";
--			attribute loc of d5: signal is "L17";		
  
end;


architecture aTP2 of TP2 is
    
  component ContadorBCD5Digitos is
  port(
	 rst : in std_logic;
	 ck: in std_logic;
	 e: in std_logic;
	 q4 : out std_logic_vector(3 downto 0);
	 q3 : out std_logic_vector(3 downto 0);
	 q2 : out std_logic_vector(3 downto 0);
	 q1 : out std_logic_vector(3 downto 0);
	 q0 : out std_logic_vector(3 downto 0)
	 );
  end component;
  
  component ffd is
  port(
    clr: in std_logic;
    ck: in std_logic;
    d: in std_logic;
    e:in std_logic;
    q: out std_logic;
    nq: out std_logic );
  end component;
  
  component latch4bits is
    port(
      ck:  in std_logic;
	    e:   in std_logic; 
	    entrada : in std_logic_vector(3 downto 0);
	    salida  : out std_logic_vector(3 downto 0)
      
 	  );
  end component;
  
  component ControladorDisplay7seg is
  port(
     bcd3,bcd2,bcd1,bcd0 : in std_logic_vector (3 downto 0);
     ck  : in std_logic;
     displayNumerico: out std_logic_vector(7 downto 0);
     selector: out std_logic_vector(3 downto 0)
  );
  end component;

  signal rst_s: std_logic:='1';
  signal d5_s,q_s: std_logic;
  signal latch_enable: std_logic;	
  signal q4_s : std_logic_vector(3 downto 0);
  signal q3_s : std_logic_vector(3 downto 0);
  signal q2_s : std_logic_vector(3 downto 0);
  signal q1_s : std_logic_vector(3 downto 0);
  signal q0_s : std_logic_vector(3 downto 0);
  signal salidaVGA1_s : std_logic_vector(3 downto 0);
  signal salidaVGA2_s : std_logic_vector(3 downto 0);
  signal salidaVGA3_s : std_logic_vector(3 downto 0);
  signal salidaVGA4_s : std_logic_vector(3 downto 0);
  
  begin
  process (ck)
    variable contadorGeneradorDeEnable : natural := 0;
  begin
    if ck'event and ck='1' then
        contadorGeneradorDeEnable := contadorGeneradorDeEnable+1 ;
        if contadorGeneradorDeEnable=33000 then 
          latch_enable<='1';
        elsif contadorGeneradorDeEnable=33001 then 
          contadorGeneradorDeEnable:= 0;
          rst_s<='1';
          latch_enable<='0';
        else
          rst_s<='0';  
        end if;
    end if;
  end process;
  d5<=d5_s;
  flipflop: ffd port map('0',ck,d6,'1',q_s,d5_s);
  contador: ContadorBCD5Digitos port map(rst_s,ck,q_s,q4_s,q3_s,q2_s,q1_s,q0_s); 
  latch4 : latch4bits port map(ck,latch_enable,q4_s,salidaVGA4_s);
  latch3 : latch4bits port map(ck,latch_enable,q3_s,salidaVGA3_s);
  latch2 : latch4bits port map(ck,latch_enable,q2_s,salidaVGA2_s);
  latch1 : latch4bits port map(ck,latch_enable,q1_s,salidaVGA1_s);
  display: ControladorDisplay7seg port map (salidaVGA1_s,salidaVGA2_s,salidaVGA3_s,salidaVGA4_s, ck, displayNumerico, selector);   
  
  salidaVGA1  <= salidaVGA1_s;
  salidaVGA2  <= salidaVGA2_s;
  salidaVGA3  <= salidaVGA3_s;
  salidaVGA4  <= salidaVGA4_s;
   

end;

